VHDL for Engineers, 1/e

VHDL for Engineers, 1/e Book Description

VHDL for Engineers teaches readers how to design and simulate digital systems using the hardware description language, VHDL. These systems are designed for implementation using programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology are also a key focus. Short presents the complex VHDL language in a logical manner, introducing concepts in an order that allows the readers to begin producing synthesizable designs as soon as possible.

1. Digital Design Using VHDL and PLDs
2. Entities, Architectures, and Coding Styles
3. Signals and Data Types
4. Data flow Style Combinational Design
5. Behavioral Style Combinational Design
6. Event-Driven Simulation
7. Test benches for Combinational Designs
8. Latches and Flip - flops
9. Multibit Latches, Registers, Counters, and Memory
10. Finite State Machines
11. ASM Charts and RTL Design
12. Subprograms
13. Packages
14. Testbenches for S equential Systems
15. Modular Design and Hierarchy
16. More Design Examples

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